The invention relates to a programmable frequency divider circuit, comprising:
p cascade-connected frequency dividing cells, a cell of rank i in the cascade performing an i.sup.th division, where i takes one of the values from 0 to (p-1), all cells being switchable between a divide-by-two mode, referred to as the normal mode, and a divide-by-three mode, referred to as the programmed mode, a cell having of arbitrary rank i comprising a first input (I.sub.i) for an input frequency signal (FI.sub.i) and a first output (O.sub.i) for an output frequency signal (FO.sub.i) to be applied to the first input (I.sub.i+1) of the next cell of rank (i+1), a second input (CI.sub.i) for an enable signal for the programmed mode, a third input (D.sub.i) for a programming signal, and a second output (CO.sub.i) for a gating signal, there being provided means for generating said gating signal from the enable signal received on the second input (CI.sub.i) of the cell i, said gating signal being applied to the second input (CI.sub.i-1) of the cell (i-1) of lower rank as an enable signal.
A prior art frequency divider circuit of this kind is known from the document FR-A-2 653 617. According to the cited document, the programmable frequency divider circuit comprises a plurality of p cascade-connected dividing cells, each of which is capable of performing a division of the input frequency of the cell by two or by three, depending on the value of signals applied on the one hand to the third input, referred to as the programming input (D.sub.i), and on the other hand to the second input (CI.sub.i) which is referred to as the enable input of the relevant cell. For a given division factor, appropriate signals are permanently applied to the programming inputs (D.sub.i), whereas an enable signal received on the second input (CI.sub.i) of each cell determines the instant at which the relevant cell must execute the division mode which is referred to as the programmed mode, i.e. a division by three instead of two in the normal mode. Each cell receiving an enable signal supplies the preceding cell with a signal which is referred to as a gating signal and which is received by said preceding cell as an enable signal.
The known frequency divider circuit has a given number of limitations. On the one hand, the range of division factor values to be utilized by such a circuit is rather limited (it depends on the number of cells), because the enable signal applied to the p.sup.th cell, i.e. the last one of the series, is actually an invariable signal and more specifically a low signal. The corresponding enable input is actually connected to ground. On the other hand, in the known circuit each dividing cell produces a gating signal intended for the preceding cell and fixed by the rhythm of that cell itself in as far as it concerns the transition to the active logic state of said gating signal, whilst the returning to the inactive logic state of this gating signal is applied directly to all cells simultaneously under the influence of an OR-gate provided in each cell of this circuit. This signal necessarily incurs a delay while progressing through the p cells of the circuit, whereas a high precision is necessary in as far as it concerns the first cell which operates at the highest frequency.
It is an object of the present invention to eliminate said limitations.